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Misra Parallelism Safety-critical Guidelines for C++11, 17, Then C++20, 23 - CppCon 2021

English --- The next revision of MISRA C++ is heavily anticipated and the group has been working at an even higher cadence since the shutdown. What you may not know is that there is also a group working on C++ parallel concurrency safety rules to be issued alongside the next MISRA.
There have been very few attempts to take parallelism in a safety critical direction even as many in the industry head towards multicore, manycore, and heterogeneous architectures. This is especially the case in the automotive, medical, and engineering industry and there has been increasing demands for these kinds of guidelines. However, most safety rules tend to focus only on sequential code. There have been a few previous attempts at defining safe parallelism rules by Autosar, High Integrity C++, several H2020 projects, as well as C++ CG, but none have produced statically checkable rules in the format of MISRA. This WG within MISRA C++ attended by safety experts with parallelism background is attempting to unify these attempts.
This talk will summarize the latest progress of this group, reviewing the rules that have the potential of entering MISRA NEXT, as well as those we deferred to a subsequent release. We will discuss the philosophy of why some rules are accepted, or rejected, or deferred. There are currently 18 rules that could be accepted, with another 20 rules that are deferred to the following release. We will speak of the challenge of being C++ parallel safety experts in our respective companies. Finally, while MISRA NEXT will likely aim for C++11, 14, 17, we look into the future, where we also aim to serve the parallelism features in C++20, 23.
--- Ilya Burylov
Ilya is an architect of C++ software solutions for autonomous driving market. He is working on contribution into functional safety standard MISRA and C++ standard bodies in threading and vectorization. Ilya has contributed into various Intel software products such as Intel DAAL and Intel MKL.
Andreas Weis
Andreas Weis has been writing C++ code in many different domains, from real-time graphics, to distributed applications, to embedded systems. As a library writer by nature, he enjoys writing portable code and exposing complex functionalities through simple, richly-typed interfaces. Both of which C++ allows him to do extensively. Andreas is also one of the co-organizers of the Munich C++ User Group, which allows him to share this passion with others on a regular basis.
Michael Wong
Michael Wong is Distinguished Engineer/VP of R&D at Codeplay Software. He is a current Director and VP of ISOCPP , and a senior member of the C++ Standards Committee with more then 15 years of experience. He chairs the WG21 SG5 Transactional Memory and SG14 Games Development/Low Latency/Financials C++ groups and is the co-author of a number C++/OpenMP/Transactional memory features including generalized attributes, user-defined literals, inheriting constructors, weakly ordered memory models, and explicit conversion operators. He has published numerous research papers and is the author of a book on C++11. He has been an invited speaker and keynote at numerous conferences. He is currently the editor of SG1 Concurrency TS and SG5 Transactional Memory TS. He is also the Chair of the SYCL standard and all Programming Languages for Standards Council of Canada. Previously, he was CEO of OpenMP involved with taking OpenMP toward Acceelerator support and the Technical Strategy Architect responsible for moving IBM’s compilers to Clang/LLVM after leading IBM’s XL C++ compiler team.
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